The present invention relates to a memory control circuit, and more particularly, to a memory control circuit for controlling the writing and reading of data to or from a memory circuit.
When digital data undergoes an error correction process or an encoding/decoding process, various computation processes are performed on the digital data in block units. At this time, one block of digital data is stored in a buffer memory for a predetermined period to perform the computation process.
FIG. 1 is a schematic block diagram of a memory control circuit 100.
A memory circuit 10 has a capacity enabling storage of at least one block of data that undergoes the computation process. The memory circuit 10 stores write data DIN provided from the memory control circuit 100 and reads the stored data. Read data DOUT is sequentially output from the memory circuit 10. The memory circuit 10 is a synchronous memory which writes and reads data in accordance with a timing clock CK.
The memory control circuit 100 includes a control signal generation circuit 1, an address generation circuit 2, and a write data supply circuit 3. In response to a data write command or a data read command provided by a microprocessor, the control signal generation circuit 1 generates a write enable signal WE, which permits a write operation to be performed in the memory circuit 10, and a read enable signal RE, which permits a read operation to be performed. The control signal generation circuit 1 also generates a timing clock CK, which determines the operational timing of the memory circuit 10. In response to an address command provided from the microprocessor together with the data write/read command, the address generation circuit 2 generates an address AD for the memory circuit 10 and provides the address AD to the memory circuit 10. The write data supply circuit 3 receives data and holds the data. The held data is provided to the memory circuit 10 as the write data DIN.
The control signal generation circuit 1 generates the write enable signal WE, the read enable signal RE, and the timing clock CK in accordance with a reference clock BCK. During the write operation, the write data supply circuit 3 provides the write data DIN to the memory circuit 10 in accordance with the reference clock BCK. The address generation circuit 2 provides the write address AD of the data DIN, at the same time as the write enable signal WE, to the memory circuit 10 in accordance with the reference clock BCK. During the read operation, the address generation circuit 2 provides the read address AD, at the same time as the read enable signal RE, to the memory circuit 10.
FIG. 2 is a timing chart illustrating the write operation performed for two consecutive data.
Write data D(n) is first held by the write data supply circuit 3 in response to the rising of the reference clock BCK. The write data D(n) is provided to the memory circuit 10 during one cycle of the reference clock BCK. Synchronously with the holding of the data D(n), the write enable signal WE rises in accordance with the write command, and a p address of the memory circuit 10 is designated by the address AD. The data D(n) is written to the p address of the memory circuit 10 in response to the rising of the timing clock CK. Data D(n+1) provided subsequent to the data D(n) is also written to the memory circuit 10 in the same manner as described above. At this time, the address AD is changed from the p address to a q address at a timing in which the write data D(n) is switched to the data D(n+1).
FIG. 3 is a timing chart illustrating the read operation of the data stored in the memory circuit 10.
In accordance with the read command, the control signal generation circuit 1 causes the read enable signal RE to rise in response to the rising of the reference clock BCK and provides an address AD designating the p address to the memory circuit 10. When the timing clock CK rises in this state, the data D(n) stored at the p address of the memory circuit 10 is read and read data DOUT is output from the memory circuit 10. In response to the next rising edge of the reference clock BCK, the timing clock CK falls, and then the address AD is changed from the p address to the q address. In this state, when the timing clock CK rises again, the data D(n+1) stored at the q address of the memory circuit 10 is read and the read data DOUT is output from the memory circuit 10.
The memory circuit 10 has the writing or reading of data repeated in cycles in accordance with the reference clock BCK. A shorter operation cycle of the memory circuit 10 is effective for increasing the speed for processing digital data. However, the operation cycle is limited within a range in which access to the memory circuit 10 is allowed.
The time required for the computation process of the digital data is determined by the access speed of the memory circuit 10, which temporarily stores the digital data during the computation process. The access speed of the memory circuit 10 is determined by delays resulting from the circuit configuration in the memory circuit 10. Thus, when the storage capacity of the memory circuit 10 is expanded and the circuit area is increased, an increase in the access speed becomes difficult. Accordingly, as the digital data increases, it becomes difficult to decrease the processing time.